As the speed, power and complexity of many of today's high performance electronic applications have increased, there has been a growing demand for increasing the packaging density on a printed wiring board, or printed circuit substrate, to accommodate a greater number of more complex components on the board. Packaging density is primarily improved by decreasing the size of and spacing between individual components on the board, such as integrated circuit chips, conductive traces, and other components which are typically found on many printed circuit assemblies.
One manner of increasing the packaging density on a printed wiring board is by utilizing a surface mount technology (SMT) such as OMPAC packaging, which is exemplified by U.S. Pat. No. 4,700,473, issued to Freyman et al. In this form of packaging, through holes are formed in the chip carrier to connect conductive traces routed on the chip carrier with solder bumps which have been formed on the back side of the carrier in a ball grid array. An unpackaged integrated circuit chip having leads disposed about its periphery is wire bonded to the conductive traces on the carrier. The OMPAC packaging as a whole is then bonded to a printed wiring board by reflowing the solder bumps to connect with corresponding contact pads on the printed wiring board.
While carrier-based processes such as OMPAC packaging have represented improvements in packaging density, the processes nonetheless suffer from a number of drawbacks, including increased real estate (packaging area), increased numbers of materials and processing steps, increased interconnect layers and connections, increased risk of failure due to potential mismatches between chip, carrier and substrate, as well as increased cost.
Other SMT processes eliminate the necessity for chip carriers and the attendant drawbacks associated therewith. One such interconnect technology utilizes direct application of flip chips to a printed wiring board. Flip chips are unpackaged integrated circuit chips that may be wirebonded to a printed wiring board, or alternatively may be soldered to a board through solder bumps disposed on the bonding pads of the chips. The active side of a flip chip contains the active devices and bonding pads, and has a passivation layer that can protect its active components from environmental contaminants. The back side of a flip chip, opposite to the active side, may contain markings indicating die part numbers and an electrical orientation for the circuit application. The flip chips are so named because they are mounted with their active side facing down towards the circuit substrate, with their solder bumps in registration with contact pads formed into a footprint on the printed circuit substrate.
A type of flip chip connection method is controlled collapsed chip connection (C-4) soldering, which involves registering the solder bumps of a flip chip on matching wettable solder contacts of the substrate, and then heating the solder to induce reflow and electrical connection between the chip and the substrate. By means of registration, I mean the placement of a flip chip on a substrate, such that each solder bump on the flip chip is located directly over its corresponding active contact pad, and such that the flip chip is in a position to be electrically connected without further movement of the flip chip or the substrate. The temperatures required to reflow the solder bumps using C-4 soldering, however, has made this process unsuitable for a number of lower cost substrates such as flexible substrates incorporating polyimide or polyester films, particularly those in which adhesives are used to bond copper circuit patterns to the substrate films.
Several other flip chip processes, however, use lower temperature solder compositions to reduce the amount of heat necessary to form interconnections between flip chips and the base substrate. For instance, U.S. Pat. No. 4,967,950 uses a thermode heat probe in contact with a flip chip to heat an eutectic alloy which has been "tinned" onto the contact pads on a substrate.
Another lower temperature process for attaching flip chips to a substrate is disclosed in U.S. Pat. No. 5,261,593, issued to Casson et al. To the extent necessary to support this disclosure, the disclosure of this reference is incorporated by reference herein.
In the Casson et al. process, a low temperature solder paste is registered on contact pads on a printed wiring board. One or more chips are then registered on the printed wiring board over the contact pads such that the solder bumps on the chips are in registration with the solder paste on the contact pads. The solder paste on each contact pad on the entire assembly is then reflowed by heating the assembly as a whole, such as in an infrared reflow oven. The solder bumps and solder paste then form homogeneous compositions which solidify to provide mechanical and electrical interconnects between the flip chips and the board.
The Casson et al. process has an advantage over other direct application technologies in that a wider variety of substrates may be used in conjunction with the process since the substrates are typically exposed to lower temperatures. One suitable substrate is a flexible adhesiveness metallized laminate such as the laminates sold under the trademark NOVACLAD.RTM. by Sheldahl, Inc. of Northfield, Minn., which are the subject of U.S. Pat. Nos. 5,112,462 and 5,137,791 to Swisher. To the extent necessary to support this disclosure, the disclosures of these references are incorporated by reference herein.
Direct chip interconnection processes may provide increases in packaging density; however, as the number of input/output connections on a chip increases, the ability to provide further improvements in packaging density with these methods become limited. In particular, higher performance chips require greater numbers of input/output connections, which in turn require larger, more expensive, and less reliable chips since input/output connections are conventionally disposed about the chips' periphery.
The number of input/output connections on a chip may be increased without increasing the overall size of the chip by providing bonding pads in a grid array over the active surface of a chip (i.e., around the periphery and in an interior area bounded by the bonding pads around the periphery). However, one drawback with this particular process is the difficulty in routing conductive traces on a single conductive layer on a substrate to the contact pads on the layer which bond with the bonding pads formed in the interior area of the chip.
For example, FIG. 2 shows a conventional single-sided grid array design. In the single-sided design, some of the conductive traces, such as conductive trace 112b which is connected to active contact pad 110b, are required to be routed between other contact pads, such as pads 110e and 110f. While routing conductive traces between contact pads is not particularly problematic for smaller grid arrays, it will be appreciated that for large arrays of contact pads (e.g., a 26.times.26 array of pads) a significant number of lines (e.g., at least 12 lines for a 26.times.26 array) would need to be routed between individual contact pads. However, the spacing required between contact pads to accommodate a large number of traces may significantly reduce the number of input/output connections which may be provided on a given size of chip. Alternatively, the required spacing between contact pads for a given number of conductive traces may require an increase in the size of the chip, which is often not economically or technologically feasible, and which is counter to the miniaturization trend in the electronics industry.
Consequently, it will be appreciated that the density of input/output connections on a flip chip (and therefore the number of connections which may be provided on a single chip) is typically limited by the minimum line spacing, line width, and number of lines which must be routed between opposing contact pads on a printed wiring board in each of the above-described processes, particularly for bonding flip chips having grid arrays of solder bumps disposed thereon.
Therefore, a need exists in the art for providing interconnections between an unpackaged integrated circuit chip and a printed wiring board which offers improved packaging density. In particular, a need exists for connecting grid array chips (i.e., chips with solder bumps arranged in a grid array, rather than being disposed about the periphery) in a manner which reduces limitations imposed by routing multiple lines between contact pads on a printed wiring board such that greater packaging density of input/output connections on unpackaged integrated circuit chips may be provided.